1. Field
Example embodiments relate to semiconductor memory devices, and more particularly, to semiconductor memory devices in which interconnection of control signal lines controlling circuits of sensing regions on which sense amplifiers and equalizers are disposed are improved, and in which the arrangement of control signal drivers activating the control signal lines are improved.
2. Description of Related Art
Semiconductor memory devices are commonly equipped with sensing regions for detecting and amplifying data transferred through bit lines. If a word line is selectively activated, the data stored memory cells that are coupled to the selected word line are transferred to the sensing region by way of bit lines. The sensing region detects and amplifies the data transferred through the bit lines, and outputs the detected and amplified data. The sensing region may include an equalizer, an NMOS sense amplifier, and a PMOS sense amplifier, each of which is operable in response to signals transferred through drive signal lines arranged in a word line direction of the device.